1. Field of the Invention
Generally, the present disclosure relates to integrated circuits and, more particularly, to silicon-on-insulator (SOI) semiconductor devices, which include substrate diodes that are formed in the crystalline material of the substrate and which include film diodes that are formed in the active semiconductor layer.
2. Description of the Related Art
The fabrication of integrated circuits requires a large number of circuit elements, such as transistors and the like, to be formed on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed above a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. These regions are embedded or are formed in a well region, which has an appropriate doping level and profile so as to adjust the basic transistor characteristics, such as threshold voltage and the like. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the distance between the source and drain regions, which is also referred to as channel length. Therefore, reducing the feature sizes and in particular the gate length of the field effect transistors has been an important design criterion.
In view of further enhancing performance of transistors, in addition to other advantages, the SOI architecture has continuously been gaining in importance for manufacturing MOS transistors due to their characteristics of a reduced parasitic capacitance of the PN junctions, thereby allowing higher switching speeds compared to bulk transistors. In SOI transistors, the semiconductor region or active region, in which the drain and source regions as well as the channel region are located, also referred to as the body, is dielectrically encapsulated. This configuration provides significant advantages, but also gives rise to a plurality of issues. Contrary to the body of bulk devices, which is electrically connected to the substrate and thus applying a specified potential to the substrate maintains the bodies of bulk transistors at a specified potential, the body or well of SOI transistors is not connected to a specified reference potential, and, hence, the body's potential may usually float due to the accumulation of minority charge carriers, unless appropriate countermeasures are taken.
A further issue in high performance devices, such as microprocessors and the like, is an efficient device-internal temperature management due to the significant heat generation of the transistors. Due to the reduced heat dissipation capability of SOI devices caused by the buried insulating layer, the corresponding sensing of the momentary temperature in SOI devices is of particular importance.
Typically, for thermal sensing applications, an appropriate diode structure may be used, wherein the characteristic of the diode may permit information to be obtained on the thermal conditions in the vicinity of the diode structure. The sensitivity and the accuracy of the respective measurement data obtained on the basis of the diode structure may significantly depend on the diode characteristic, i.e., on the diode's current/voltage characteristic, which may depend on temperature and other parameters. For thermal sensing applications, it may, therefore, typically be desirable to provide a substantially ideal diode characteristic in order to allow a precise estimation of the temperature conditions within the semiconductor device. In SOI devices, a corresponding diode structure, i.e., the respective PN junction, is frequently formed in the substrate material located below the buried insulating layer, above which is formed the active semiconductor layer used for forming therein the transistor elements. Thus, at least some additional process steps may be required, for instance, for etching through the semiconductor layer or a corresponding trench isolation area and through the buried insulating layer in order to expose the crystalline substrate material. On the other hand, the process flow for forming the substrate diode is typically designed so as to exhibit a high degree of compatibility with the process sequence for forming the actual circuit elements, such as the transistor structures.
During the development of very sophisticated semiconductor devices on the basis of an SOI architecture, however, diode structures formed in the crystalline substrate material may provide valuable information, for instance with respect to the thermal state of the substrate material, wherein, however, an accurate assessment of the general thermal conditions in the device level, i.e., in the semiconductor layer formed above the buried insulating material, may be difficult since the heat dissipation through the buried insulating material, which may have a significantly lower thermal conductivity compared to a silicon material, may result in a pronounced temperature gradient between the active semiconductor layer and the substrate material. To this end, frequently, additional diode structures may also be used for other purposes, such as providing appropriate discharge paths for electrostatic discharge events (ESD) and the like. The substrate diodes formed in the active semiconductor layer, which may also be referred to as a “film diode,” may also require specifically selected diode characteristics in order to obtain the desired function, for instance, for obtaining representative information on the thermal conditions within the active semiconductor layer. Generally, the PN junction for the diode structures may be formed on the basis of an appropriate well dopant concentration in combination with a corresponding inversely doped region, which is typically formed together with drain and source regions of transistors to be formed in the active semiconductor layer in order to reduce the number of required lithography steps. Since the well dopant implantation processes for the diode structures in the active semiconductor layer and in the buried crystalline substrate material have to be performed on the basis of very different implantation parameters, in conventional process strategies, therefore, the well dopant concentration of the diode structure in the active semiconductor layer may be established in a common process sequence for incorporating the well dopant species of certain types of transistors in order to not unduly increase the number of lithography steps. A typical conventional process flow will be described in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in a manufacturing phase in which the basic well dopant concentration profiles are to be established for any diode structures and transistor elements of the device 100. As shown, the device 100 is an SOI device comprising a substrate 101, which may thus comprise a crystalline semiconductor material 101S, for instance in the form of a silicon material. Moreover, a buried insulating layer 102, such as a silicon dioxide layer, is formed on the crystalline substrate material 101S with an appropriate thickness. Furthermore, a semiconductor layer 103, which may also be referred to as an active semiconductor layer, is formed on the buried insulating layer 102. It should be appreciated that the term semiconductor layer is to enclose an initial state of the layer 103, in which a substantially continuous semiconductor material is formed above the buried insulating layer 102, and is also to enclose the semiconductor layer 103 in a further process state in which a plurality of semiconductor islands or regions may be formed by providing appropriately sized isolation regions (not shown), which may thus appropriately laterally delineate corresponding semiconductor regions. For example, corresponding portions of the semiconductor layer 103, as indicated by 103A, 103B, 103C, may be provided in the manufacturing stage shown, wherein at least the regions 103B, 103C may represent actual semiconductor regions, while the region 103A may be a semiconductor material or may be a portion of an isolation region, such as a silicon dioxide region, depending on the overall process and device requirements. It should be appreciated that any isolation regions may also be formed in a later manufacturing stage, if considered appropriate for the further processing of the device 100.
Furthermore, in the manufacturing stage shown, an implantation mask 104, such as a resist mask, is formed above the semiconductor layer 103 and has an appropriate thickness so as to provide the ion blocking capability as is required to avoid penetration of the regions 103B, 103C by any well dopant species that are to be incorporated into the crystalline semiconductor material 101S at a position and with a lateral shape, which are determined by a mask opening 104A of the implantation mask 104.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following processes. The regions 103A, 103B and 103C may be defined in shape and position by forming respective isolation regions, as discussed above, which may be accomplished by using sophisticated lithography techniques, etch processes, deposition processes, anneal techniques and material removal processes. In other cases, the lateral shape and position of the regions 103A, 103B, 103C may be defined on the basis of the implantation mask 104 and on the basis of any subsequently formed implantation masks, when corresponding isolation regions are to be provided in a later manufacturing stage. Next, the implantation mask 104 is provided on the basis of appropriate lithography masks and process techniques in which the opening 104A is provided with a desired lateral size and shape so as to define a region 101A in the crystalline substrate material 101S in which a desired well dopant concentration is to be established in view of forming a diode structure on the basis of the region 101A. To this end, an implantation process 105 is performed by using appropriate energy and dose parameters so as to implant a desired dopant species, such as an N-type dopant species and the like, through the layers 103 and 102 into the region 101A. On the other hand, undue incorporation of the well dopant species in the regions 103B, 103C may be suppressed by the implantation mask 105.
FIG. 1b schematically illustrates the device 100 in a further advanced manufacturing stage. As illustrated, a further implantation mask 106 is formed above the semiconductor layer 103 and comprises appropriate mask openings 106B, 106C, thereby exposing the regions 103B, 103C. The region 103B may correspond to a certain type of transistor to be formed in and above the semiconductor region 103B, while the region 103C corresponds to a semiconductor region in which a diode structure is to be formed. As discussed above, generally it would be preferable to adjust the basic dopant concentration in the regions 103B, 103C independently from each other in order to provide superior flexibility in appropriately adjusting the transistor characteristics and the diode characteristics. On the other hand, this superior degree of flexibility is associated with at least one further lithography step, since corresponding dedicated implantation masks would be required, while also two separate implantation processes have to be performed. Since, in particular, the additional lithography step may contribute to a reduced overall throughput, typically the mask 106 is provided so as to concurrently expose the regions 103B, 103C to an implantation process 107, which is appropriately configured so as to obtain a basic dopant concentration in the regions 103B, 103C that enables the formation of transistors and of a diode structure, however, at the cost of a reduced performance, since the resulting well dopant concentration is a compromise between desired transistor characteristics and a desired ideal diode characteristic. It should be appreciated that the implantation mask 106 may not necessarily have to cover the region 103A if a corresponding incorporation of the well dopant species is considered as acceptable.
FIG. 1c schematically illustrates a cross-sectional view of the semiconductor device 100 in a further advanced manufacturing stage. As shown, a first or substrate diode 130 is formed in the region 101A, while a second diode 150 is formed in the region 103C. Furthermore, a transistor 140 is formed in and above the semiconductor region 103B. Moreover, electrode structures 160A, 160B, 160C may be formed above the regions 103A, 103B, 103C, respectively. For example, the gate electrode structure 160B may represent a part of the transistor 140 and may have any appropriate configuration and length in accordance with the overall transistor characteristics. Furthermore, drain and source regions 141 are formed in the active region 103B and form appropriate PN junctions with the remaining portion or well region 103B so as to obtain transistor characteristics which are thus determined, among other things, by the lateral and vertical profile of drain and source regions 141 and of the basic well dopant concentration of the region 103B, as adjusted on the basis of the implantation process 107 of FIG. 1b. Similarly, a diode structure 150 may comprise doped regions 151A, 151B, for instance in the form of a P-type region and an N-type region, so as to form one PN junction with the well region 103C so as to obtain a diode structure. For example, the regions 103B, 103C may be regions of N-type conductivity so that one of the regions 151A, 151B may be a highly P-doped region, thereby forming a PN junction. In this case, the transistor 140 may represent a P-channel transistor. Since typically the corresponding regions 151A, 151B may be formed together with implantation techniques as are also typically applied in the transistor 140 and in transistors of inverse conductivity type, the resulting characteristics of the diode 150 are also determined by the well dopant concentration in the region 103C and the lateral and vertical dopant profile of the regions 151A, 151B, respectively. In this case, the resulting diode characteristics may represent a compromise with respect to the desired transistor characteristics of, for instance, the device 140.
On the other hand, the substrate diode 130 may have characteristics that are determined by the well dopant concentration in the region 101A, while the dopant profile of highly doped regions 131A, 131B may also be formed together with the drain and source regions of any transistors, such as the transistor 140 and a transistor of inverse conductivity type, so that basically the diode characteristics may also be influenced by the process techniques used for forming the transistors, wherein, however, contrary to the diode 150, the well dopant concentration in the region 101A may be individually adjusted on the basis of the implantation process 105 (FIG. 1a).
Generally, the device 100 may be formed on the basis of any appropriate process strategy, i.e., appropriate materials for the electrode structures 160A, 160B, 160C may be formed, for instance, by oxidation, deposition and the like, and these materials may be patterned on the basis of sophisticated lithography techniques in order to obtain, in particular, the gate electrode structure 160B with the required lateral dimensions, for instance having a gate length of 50 nm and less in sophisticated applications. For example, a gate dielectric material 161 in combination with an electrode material 162, possibly together with appropriate hard mask materials, are patterned, followed by the formation of an appropriate sidewall spacer structure 163, which may also act as an implantation mask when forming the complex lateral and vertical dopant profiles in the transistors of the device 100. At any appropriate stage, an etch process may be performed to expose portions of the region 101A, in which the highly doped regions 131A, 131B are to be provided together with drain and source regions of transistors by using appropriate implantation and masking regimes in order to incorporate a dopant species of one conductivity type in one of the regions 131A, 131B and introducing a dopant species of inverse conductivity type in the other one of the regions 131A, 131B. Furthermore, the regions 151A, 151B may also be formed in the same process sequence, depending on the overall process strategy.
Thereafter, the processing is continued by performing any appropriate anneal processes and, if required, forming metal silicide regions in the highly doped regions of the diodes 130, 150 and in the transistor 140.
Consequently, the process sequence described above provides a very efficient process flow, however, it requires a compromise in performance of the film diode 150 due to the combined formation of a well dopant concentration in the regions 103B, 103C. In sophisticated applications, however, performance of the transistor 140 and/or performance of the diode 150 is to be enhanced which, however, may not be compatible with the conventional process strategy, while separating the implantation processes for forming the well dopant concentration in the regions 103B, 103C may require additional lithography steps.
In view of the situation described above, the present disclosure relates to manufacturing techniques and semiconductor devices in which diode structures in a substrate material and an active semiconductor material may be formed, while avoiding or at least reducing one or more of the problems identified above.